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| d a t a sh eet preliminary speci?cation file under integrated circuits, ic01 1998 mar 10 integrated circuits SAA2505H digital multi-channel audio ic (duet)
1998 mar 10 2 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H features hardware features two 40 mips 20-bit dsp cores all input and output buffer ram is on-chip program rom on-chip for all decoding modes two i 2 s-bus inputs with normal, double and quad speed mode (slave only) second serial input usable for adc (karaoke input) three normal and double speed i 2 s-bus outputs (slave and master from 256 and 384f s ) one normal, double, quad speed i 2 s-bus output (slave and master from 256 and 384f s ) japanese eiaj serial input and output formats sony philips digital interface (spdif) output i 2 c-bus control (up to 400 khz) 3.3 v supply with 5 v ttl compatible inputs/outputs boundary scan for printed-circuit board testing. software features ac-3 up to 5.1 channels mpeg 2 l2 up to 7.1 channels mpeg 1 l2 (video-cd) 2 channels at 44.1 khz dolby pro-logic decoding at 32, 44.1 and 48 khz output configuration for 7, 5, 4, 3, 2 and 1 channels with or without low frequency enhancement (lfe) bass redirection for small satellite loudspeakers plus subwoofer karaoke voice mix dynamic range compression (ac-3 and mpeg) adjustable delay up to 15 ms for surround channels (1.5 kbyte words) adjustable delay up to 5 ms for centre channel (250 words) rounding to dac word length mute by pin and i 2 c-bus command ac-3 and mpeg bitstream information available via the i 2 c-bus concealment of crc errors spdif coded output fully programmable spdif channel status information. applications the SAA2505H is intended for all markets where a multi-channel audio decoder for dolby ac-3 and mpeg 2 is required. primary markets are for dvd video players, tv sets and audio/video amplifiers. general the SAA2505H decodes multi-channel audio up to mpeg 7.1, ac-3 5.1 and pro-logic on a dual dsp core. the device contains all of the ram and rom necessary for operation. this minimises the need for external components and no microcode download is required. the device is primarily intended for audio/video surround sound amplifiers where the amplifier is connected to the data source by means of spdif (iec 60958). the input interface is, therefore, made for spdif (iec 60958) and formatted for the i 2 s-bus. the primary device output is pcm, sent via four i 2 s-bus ports. there is also a spdif (iec 60958) formatted output. user control is achieved via an i 2 c-bus. however, the SAA2505H is capable of stand-alone operation. 1998 mar 10 3 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H quick reference data notes 1. human body model: equivalent to discharging a 100 pf capacitor through a 1500 w resistor. 2. machine model: equivalent to discharging a 200 pf capacitor through a 0 w resistor. ordering information symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current - 160 - ma v dda analog supply voltage 3.0 3.3 3.6 v i dda analog supply current - tbf - ma f xtal crystal frequency - 35 - mhz t amb operating ambient temperature 0 - 70 c v esd electrostatic discharge sensitivity for all pins note 1 - 2000 - +2000 v note 2 - 300 - +300 v type number package name description version SAA2505H qfp64 plastic quad ?at package; 64 leads (lead length 1.6 mm); body 14 14 2.7 mm sot393-1 1998 mar 10 4 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... block diagram fig.1 simplified block diagram. o k, full pagewidth iis0 i 2 s-bus interface bitstream iec 1397 parser pro logic noise generator mpeg2 or ac-3 decoder switch down- mixing and volume control delay audio clock 256 or 384f s pcm and down- sampling iis1 bitstream e.g. from microphone l 8 channels 8 channels microphone l, r, c, s r c lfe ls lt, rt rs lc rc channels 1 to 8 channels 1 to 8 i 2 s-bus outputs spdif l, r bitstream down- mixing mgl324 1998 mar 10 5 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H pinning symbol pin drive/ load (1) type description standalone 1 a i select stand-alone mode input efo1 2 f o output ?ag fo1; from dsp2 efo2 3 f o output ?ag fo2; from dsp2 efo3 4 f o output ?ag fo3; from dsp2 efo4 5 f o output ?ag fo4; from dsp1 efo5 6 f o output ?ag fo5; from dsp1 efo6 7 f o output ?ag fo6; from dsp1 v ssdi 8 - s digital ground for internal logic and memories; note 2 v dddi 9 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 efi1 10 a i input ?ag fi1; to dsp2 efi2 11 a i input ?ag fi2; to dsp1 efi3 12 a i input ?ag fi3; to dsp1 v ddde 13 - s digital supply voltage for i/o cells (+3.3 v); note 4 wso 14 g i/o word select input/output for ports 0 to 2; also used for output port 3 when not in quad mode (i 2 s-bus) sck 15 g i/o serial clock input/output for ports 0 to 2; also used for output port 3 when not in quad mode (i 2 s-bus) v ssde 16 - s digital ground for i/o cells; note 5 sdo0 17 f o serial data output for port 0 (i 2 s-bus) sdo1 18 f o serial data output for port 1 (i 2 s-bus) v ddde 19 - s digital supply voltage for i/o cells (+3.3 v); note 4 v ssdi 20 - s digital ground for internal logic and memories; note 2 v dddi 21 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 v ssdi 22 - s digital ground for internal logic and memories; note 2 v dddi 23 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 v dddi 24 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 v ssdi 25 - s digital ground for internal logic and memories; note 2 v ddde 26 - s digital supply voltage for i/o cells (+3.3 v); note 4 sdo2 27 f o serial data output for port 2 (i 2 s-bus) sdo3 28 f o serial data output for port 3 (i 2 s-bus) v ssde 29 - s digital ground for i/o cells; note 5 wso3 30 f o word select output for port 3; used in quad mode (i 2 s-bus) scko3 31 f o serial clock output for port 3; used in quad mode (i 2 s-bus) v ddde 32 - s digital supply voltage for i/o cells (+3.3 v); note 4 sdb 33 f o serial data begin output for port 3; used in quad mode (i 2 s-bus) spdif 34 f o spdif output v ssde 35 - s digital ground for i/o cells; note 5 v ssdi 36 - s digital ground for internal logic and memories; note 2 v dddi 37 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 1998 mar 10 6 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H notes 1. see table 1. 2. all v ssdi pins are internally connected. 3. all v dddi pins are internally connected. 4. all v ddde pins are internally connected. 5. all v ssde pins are internally connected. v ssde 38 - s digital ground for i/o cells; note 5 sysclk 39 e o programmable system clock output v ddde 40 - s digital supply voltage for i/o cells (+3.3 v); note 4 v dda 41 - s analog supply voltage for crystal oscillator (+3.3 v) clki 42 h i oscillator input clko 43 h o oscillator output v ssda 44 - s digital ground for crystal oscillator aclk 45 a i audio clock input for master mode v ssde 46 - s digital ground for i/o cells; note 5 tdi 47 b i boundary scan test data input (this pin should be pulled high for normal operation) tms 48 b i boundary scan test mode select input (this pin should be pulled high for normal operation) tck 49 b i boundary scan test clock input trst 50 b i boundary scan test reset input (this pin should be pulled low for normal operation) tdo 51 b o boundary scan test data output v dddi 52 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 v ssdi 53 - s digital ground for internal logic and memories; note 2 wsi 54 a i word select input for ports 0 and 1 (i 2 s-bus) sdbi 55 a i serial data begin input for port 0 (i 2 s-bus) sdi0 56 a i serial data input for port 0 (i 2 s-bus) sdi1 57 a i serial data input for port 1 (i 2 s-bus) scki 58 a i serial clock input for ports 0 and 1 (i 2 s-bus) v ssdi 59 - s digital ground for internal logic and memories; note 2 v dddi 60 - s digital supply voltage for internal logic and memories (+3.3 v); note 3 reset 61 c i hardware reset addr 62 a i select address input (i 2 c-bus) scl 63 c i serial clock input; external pull-up to +5 v (i 2 c-bus) sda 64 d i/o serial data input/output; external pull-up to +5 v (i 2 c-bus) symbol pin drive/ load (1) type description 1998 mar 10 7 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H table 1 pin drive and load descriptions drive/load description a +5 v tolerant input; ttl characterized with internal pull-down resistor b +5 v tolerant input; ttl characterized with internal pull-up resistor c +5 v tolerant input; ttl schmitt-trigger characterized d +5 v tolerant 400 khz (i 2 c-bus) e ttl characterised +5 v tolerant 3-state output with 3 ma drive capability f ttl characterised +5 v tolerant 3-state slew rate limited output with 3 ma drive capability g +5 v tolerant bidirectional 3-state pin; with 3 ma output drive and slew rate limiting; ttl level input; without pull-up or pull-down resistor h crystal pins fig.2 pin configuration. handbook, full pagewidth SAA2505H mgl323 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 tms tdi v ssde aclk v ssda clko clki v dda v ddde sysclk v ssde v dddi v ssdi v ssde spdif sdb standalone efo1 efo2 efo3 efo4 efo5 efo6 v ssdi v dddi efi1 efi2 efi3 v ddde wso sck v ssde 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 sda scl addr reset v dddi v ssdi scki sdi1 sdi0 sdbi wsi v ssdi v dddi tdo trst tck sdo0 sdo1 v ddde v ssdi v dddi v ssdi v dddi v dddi v ssdi v ddde sdo2 sdo3 v ssde wso3 scko3 v ddde 49 1998 mar 10 8 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H clock build-up up to four clocks provide the timing information for the SAA2505H. these are as follows: 1. data source clock 2. data processing clock 3. i 2 c-bus data/control clock 4. data sink clock. data source clock clocking of the input data is derived from the serial clock input at pin 58 and is compliant with the i 2 s-bus and eiaj transfer formats. the ports are capable of operating at normal, double and quad speed. data processing clock this clock is used for data processing and internal data transfer. the clock can either be provided by an external clock generator having a duty cycle between 40 and 60% or by using the internal crystal clock generator and an external crystal. the external clock should be connected between pins 42 (clki) and 43 (clko) (see fig.11). to use the internal clock a 35 mhz crystal operating on the 3rd harmonic must be connected between pins 42 and 43 (clki and clko). a buffered version of this clock is available at pin 39 (sysclk). this can be optionally disabled or, a divided version (4, 2 and 1) of the clock input at pin 42 (clki) can be made available. i 2 c-bus data/control clock the i 2 c-bus control logic supports i 2 c-bus clock speeds up to 400 khz. this is supplied to pin 63 (scl). if the SAA2505H is in the stand-alone mode (pin 1 high) no i 2 c-bus clock needs to be supplied. data sink clock the data sink clock source is dependant on the mode of operation of the i 2 s-bus output ports. in the master mode the i 2 s-bus clock is derived form an external 256 or 384f s source connected to pin 45 (aclk). this is internally divided and used to drive the serial clock at pins 15 and 31 (sck and scko3). to ensure that the digital outputs poses good timing qualities (jitter and wander) pin 45 should be a connected to a high quality timing source. in the i 2 s-bus slave mode the output data is clocked to pin 15. this can either be the serial clock input at pin 58 (scki) or a suitable external clock. when in slave mode the signal at pin 15 is replicated at pin 31. functional description data sinks coded audio data or pcm audio data can be input to both dsps from two slave-only serial interfaces capable of receiving data in either i 2 s-bus or eiaj formats. both serial interfaces use the same serial clock (pin 58) and word select input (pin 54). the serial clock must be at least 32f s . serial data is applied to pins 56 and 57 (sdi0 and sdi1). these pins are mode shared between the i 2 s-bus and eiaj formatted serial data. port mode selection is achieved via the i 2 c-bus interface, see table 3. i 2 s- bus formatted spdif information in the i 2 s-bus mode big-endian data is received, msb justified to 1 clock period after a falling edge of the word select output. the data stream should be formatted according to iec 60958 - spdif including the extensions for non-pcm encoded audio data ( iec 61937 ). ac-3 and mpeg coded data is formatted in 16-bit words. these words are expected at a sample rate (f s ) of 48 khz and thus a minimum serial clock of 1.536 mhz; two 16-bit words per word select period. if the transmission word length is in excess of 16 bits all additional bits are discarded. pcm sample lengths of up to 20-bit words are supported with sample rates of 44.1 and 48 khz. this mode is used to transfer pcm and pcm with dolby pro-logic encoded data. word select low corresponds to transmission of data for the left channel, word select high corresponds to transmission of data for the right channel. pin 55 (sdbi) is reserved for a multi-channel extension to the i 2 s-bus and is currently not supported. 1998 mar 10 9 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H eiaj formatted inputs in eiaj mode big-endian data is received lsb justified to the rising edge of word select output. formatting of the data is identical to that used in the i 2 s-bus mode. fig.3 i 2 s-bus format (msb fixed). handbook, full pagewidth mgl327 first read write sck sd msb ws msb - 1 second read write sck sd msb ws msb - 1 lsb lsb + 1 fig.4 eiaj format (lsb justified). handbook, full pagewidth mgl328 first first read write sck sd ws second read write sck sd lsb ws lsb + 1 lsb lsb + 1 1998 mar 10 10 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H data sources i 2 s- bus and eiaj formatted outputs the device has four i 2 s-bus/eiaj mode select outputs. these outputs are capable of outputting data in eiaj 20, 18 or 16-bit and i 2 s-bus modes. the eiaj outputs are capable of operating in single or double speed, the i 2 s-bus output is capable of operating in single, double and quad speed. the output ports can either be in the slave or master mode. in the slave mode they can either be slaved to the i 2 s-bus serial clock input (pin 15) or to an external clock. in the master mode an audio clock is applied to pin 45 that is 256 or 384f s . the master clocking scheme allows the support of a 96 khz sample rate dac by use of the double speed output option. the quad speed output option is intended to allow multiple SAA2505H devices to be connected together. in order to obtain a high quality digital output in the master mode the audio clock should be of high quality, having low jitter and an even mark space ration. spdif formatted output the spdif output can transmit either coded data, as received from the serial data input at pin 56 (sdi0), or down-mixed 20-bit pcm stereo. the down-mixed stereo may be pro-logic encoded. together with the pcm samples additional control bits are transmitted. these are the channel status, user data and validity bits. the first five bytes of the channel status bits are user programmable, all following bytes are zeroed automatically. transmission is lsb first. the user data can carry message lengths of 129 bytes. these are transmitted over the spdif port at a rate of 2 bits per stereo sample. the message buffer of 129 bytes is loaded via the i 2 c-bus, if no message is written the SAA2505H outputs all zeros for the user data. table 2 output port timing information mode audio clock sampling frequency word select sampling frequency serial clock sampling frequency serial data begin sampling frequency single 256 or 384f s 1f s 64f s - double 256 or 384f s 2f s 128f s - quad 256f s 4f s 256f s 1f s quad 384f s 4f s 192f s 1f s control inputs the SAA2505H can be operated in two stand-alone modes or can be managed by the i 2 c-bus. s tand - alone modes two stand-alone modes exist to allow the device to be used in systems without a microcontroller. these two modes are standalone (pin 1) held high and standalone connected to reset (pin 61). when pin 1 is low a reset defaults the outputs to quiet, however when pin 1 is high a reset defaults the i 2 s-bus output to active and the spdif output to mute. when pin 1 is high some of the i 2 c-bus registers cannot be accessed see table 3. i 2 c- bus register control the i 2 c-bus port supports 5 v, 400 khz operation. the details of the registers are given in table 3. 1998 mar 10 11 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... table 3 i 2 c-bus control register section register name memory address default value description 1 (1) 2 (2) 3 (3) general soft_reset $8 000-b0 0 0 0 0: operation 1: reset general sysclcken $8 000-b1 0 note 4 1 0: enable sysclk output 1: disable sysclk output general sysclkdiv $8 000-b3 and b2 00 note 4 10 00: sysclk = 1 4 clk 01: sysclk = 1 2 clk 10: sysclk = clk 11: reserved general en_inp_int_dsp1 $8 000-b4 0 note 4 1 0: disable input interrupts on dsp1 1: enable input interrupts on dsp1 general en_outp_int_dsp1 $8 000-b5 0 note 4 0 0: disable output interrupts on dsp1 1: enable output interrupts on dsp1 general en_inp_int_dsp1 $8 000-b6 0 note 4 1 0: disable input interrupts on dsp2 1: enable input interrupts on dsp2 general en_outp_int_dsp1 $8 000-b7 0 note 4 0 0: disable output interrupts on dsp2 1: enable output interrupts on dsp2 general aclksel $8 000-b8 0 note 4 0 0: aclk = 256f s 1: aclk = 384f s general memconfig $8 000-b9 0 note 4 0 0: program memory on dsp1 = 12 kbytes 0: program memory on dsp2 = 8 kbytes 1: program memory on dsp1 = 8 kbytes 1: program memory on dsp2 = 12 kbytes i 2 scontrol iismode $8 001-b1 and b0 00 note 4 00 00: i 2 s-bus/eiaj input format 01: reserved 10: reserved 11: reserved i 2 scontrol iisinp $8 001-b2 0 note 4 0 0: i 2 s-bus input format 1: eiaj 16-bit input format i 2 scontrol iisi_sdb_en $8 001-b3 0 note 4 0 0: sdbi is dsp1 input ?ag 1: sdbi is aligned to ws to allow multi-channel i 2 s-bus input 1998 mar 10 12 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... i 2 scontrol reserved $8 001-b4 0 note 4 0 reserved i 2 scontrol iisoutmod $8 001-b6 and b5 00 note 4 00 00: i 2 s-bus format data output 01: eiaj 16-bit format data output 10: eiaj 18-bit format data output 11: eiaj 20-bit format data output i 2 scontrol iisoutmst $8 001-b7 0 note 4 0 0: i 2 s-bus outputs are slaves 1: i 2 s-bus outputs are masters i 2 scontrol iisoutspd $8 001-b8 0 note 4 0 0: i 2 s-bus outputs 0 to 2 operate at normal speed 1: i 2 s-bus outputs 0 to 2 operate at double speed i 2 scontrol iis3outspd $8 001-b10 and b9 00 note 4 00 00: i 2 s-bus output 3 operates at normal speed 01: i 2 s-bus output 3 operates at double speed 10: i 2 s-bus output 3 operates at quad speed 11: i 2 s-bus output 3 operates at normal speed i 2 scontrol iiso0en $8 001-b11 0 note 4 1 0: sdo0 output 3-stated 1: sdo0 output enabled i 2 scontrol iiso1en $8 001-b12 0 note 4 1 0: sdo1 output 3-stated 1: sdo1 output enabled i 2 scontrol iiso2en $8 001-b13 0 note 4 1 0: sdo2 output 3-stated 1: sdo2 output enabled i 2 scontrol iiso3en $8 001-b14 0 note 4 1 0: sdo3 output 3-stated 1: sdo3 output enabled i 2 scontrol iis3clken $8 001-b15 0 note 4 0 0: scko3, wso3 and sdb outputs 3-stated 1: scko3, wso3 and sdb outputs enabled spdif1 spdifval $8 002-b0 0 0 0 0: spdif validity bit = 0 1: spdif transmitting valid pcm spdif1 spdifbyp $8 002-b1 0 0 0 0: output pcm data from dsp1 1: output i 2 s-bus data from i 2 s-bus input spdif1 iisubit $8 002-b2 0 0 0 reserved spdif1 spdifen $8 002-b3 0 0 0 0: 3-state spdif output and reset spdif block 1: enable spdif output section register name memory address default value description 1 (1) 2 (2) 3 (3) 1998 mar 10 13 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... notes 1. standalone held low. 2. standalone held high. 3. standalone connected to reset. 4. controlled by dsp; no i 2 c-bus access. all unused bits return a value of 0. normal usage spdif1 csbyte0 $8 002-b15 to b8 0000 0000 b8: consumer mode b9: lpcm b10: copy protection b11 to b13: pre-emphasis b14 to b15: mode spdif2 csbyte1 $8 003-b7 to b0 0000 0000 b0 to b7: category code spdif2 csbyte2 $8 003-b15 to b8 0000 0000 b8 to b11: source b12 to b15: channel number spdif3 csbyte3 $8 003-b7 to b0 0000 0000 b0 to b3: source b4 to b6: clock accuracy spdif3 csbyte4 $8 003-b15 to b8 0000 0000 b0 to b3: word length section register name memory address default value description 1 (1) 2 (2) 3 (3) 1998 mar 10 14 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H i 2 c-bus control and commands (pins 63 and 64) i ntroduction a general description of the i 2 c-bus and how to use it can be obtained from philips sales offices using ordering number 9398 393 40011. for the external control of the SAA2505H a fast i 2 c-bus is implemented. this is a 400 khz bus which is downward compatible with the standard 100 khz bus. there are two different types of control instructions: instructions to control the dsp program; programming the coefficient ram and reading the values of parameters instructions controlling source selection and programmable parts; through the control registers as detailed in table 3. the detailed description of the i 2 c-bus and commands is given in the following sections. c haracteristics of the i 2 c- bus the i 2 c-bus is for 2-way, 2-line communication between different ics or modules. the two lines are the serial data line (sda) and the serial clock line (scl). both lines must be connected to the supply rail via a pull-up resistor when connected to the output stages of a microcontroller. for a 400 khz i 2 c-bus, the recommendation from philips semiconductors must be followed (e.g. up to loads of 200 pf on the bus a pull-up resistor can be used, between 200 and 400 pf a current source or switched resistor must be used). data transfer can only be initiated when the bus is not busy. b it transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals. the maximum clock frequency is 400 khz. to be able to run at this high frequency all of the inputs and outputs connected to the bus must be designed for this high speed i 2 c-bus according the philips specification (see fig.5). start and stop conditions both data and clock line will remain high when the bus in not busy. a high-to-low transition of the data line while the clock is high is defined as a stop condition (p) (see fig.6). a low-to-high transition of the data line while the clock is high is defined as a start condition (s) (see fig.6). d ata transfer a device generating a message is a transmitter, a device receiving a message is the receiver. the device that controls the message is the master and the devices which are controlled by the master are the slaves (see fig.7). a cknowledge the number of data bits transferred between the start and stop conditions from the transmitter to the receiver is not limited. each byte of 8 bits is followed by one acknowledge bit. the acknowledge bit is a high level left on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed must generate an acknowledge after the reception of each byte. also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges has to pull-down the sda line, left high by the transmitter, during the acknowledge clock pulse, so that the sda line is stable low during the high period of the acknowledge related clock pulse. set-up and hold times must be taken into account. a master receiver must signal an end-of-data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this event the transmitter must leave the data line high to enable the master to generate a stop condition (see fig.8). s tate of the i 2 c- bus interface during and after power - on reset during power-on reset the internal sda line is kept high and the sda pin is therefore high impedance. the sda line remains high until a master pulls it down to initiate communication. 1998 mar 10 15 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H fig.5 bit transfer on the i 2 c-bus. handbook, full pagewidth mbc621 data line stable; data valid change of data allowed sda scl fig.6 start and stop conditions. handbook, full pagewidth mbc622 sda scl p stop condition sda scl s start condition 1998 mar 10 16 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H fig.7 data transfer on the i 2 c-bus. handbook, full pagewidth mbc601 p s sda scl start condition stop condition 1 2 3 - 8 9 ack 9 ack 78 12 msb acknowledgement signal from receiver byte complete, interrupt within receiver clock line held low while interrupts are serviced acknowledgement signal from receiver fig.8 acknowledge on the i 2 c-bus. handbook, full pagewidth mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master 1998 mar 10 17 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H i 2 c-bus format a ddressing before any data is transmitted on the i 2 c-bus, the device which should respond is addressed first. the addressing is always done with the first byte transmitted after the start procedure. s lave address selection ( pin 62) the SAA2505H acts as slave receiver or a slave transmitter. therefore the clock signal (scl) is only an input signal. the data signal (sda) is a bidirectional line. the SAA2505H slave addresses are shown in table 4. table 4 i 2 c-bus address the subaddress bit a0 corresponds to the hardware address at pin 52 which allows the device to have 2 different addresses. this allows control of two duet ics via the same i 2 c-bus. w rite and read cycles the i 2 c-bus configuration for a write cycle is shown in table 5. the write cycle is used to write the bytes to memory and control registers. the i 2 c-bus configuration for a read cycle is shown in table 6. the read cycle is used to read bytes from memory and control registers. i 2 c-bus level i 2 c-bus address 1 59h 0 58h table 5 i 2 c-bus write sequence i 2 c-bus master SAA2505H start - i 2 c-bus address of SAA2505H - write - - acknowledge address high part - - acknowledge address low part - - acknowledge data high part - - acknowledge data medium part - - acknowledge data low part - - acknowledge data high part - - acknowledge data medium part - - acknowledge data low part - - acknowledge continued exchanges stop condition - 1998 mar 10 18 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H table 6 i 2 c-bus read sequence all ram and peripheral registers are mapped into a common 16-bit address range. the data words are all msb padded to 24-bit, however, the on-chip ram is 20-bit and therefore the 4 msbs are padded with zeros. i 2 c-bus master SAA2505H start - i 2 c-bus address of SAA2505H - write - - acknowledge address high part - - acknowledge address low part - - acknowledge start - i 2 c-bus address of SAA2505H - read - - acknowledge - data high part - acknowledge - data medium part - acknowledge - data low part - acknowledge - data high part - acknowledge - data medium part - acknowledge - data low part - acknowledge continued exchanges stop condition - table 7 SAA2505H i 2 c-bus address ranges power supply connections and emc the digital part of the chip has in total 13 positive supply line connections and 13 ground connections. to minimise radiation the device should be put on a double layer pcb with, on one side, a large ground plane. the ground supply lines should have a short connection to this ground plane. the supply line connections should have minimum inter-pin pcb track impedances. a low reactance (q) ferrite bead/capacitor network in the positive supply line can be used as a high frequency filter. special attention should be paid to the analog supply lines (v dda and v ssa ). boundary scan test interface the SAA2505H has a 5 pin boundary scan test interface which implements the three required commands of the ieee1149; bypass, sample and extest. the boundary scan test interface uses the following pins tdi (pin 47), tms (pin 48), tck (pin 49), trst (pin 50) and tdo (pin 51). naming and use of the pins is as per ieee recommendations. though trst, tms and tdi have internal pull-up resistors there should also be system level pull-up resistors. start stop memory block $0 $1fff dsp1 x memory $2000 $3fff dsp1 y memory $4000 $5fff dsp2 x memory $6000 $7fff dsp2 y memory $8000 $9fff control registers 1998 mar 10 19 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model: equivalent to discharging a 100 pf capacitor through a 1500 w resistor. 2. machine model: equivalent to discharging a 200 pf capacitor through a 0 w resistor. thermal characteristics characteristics digital i/o at t amb = 0 to 70 c; v ddd = 3.0 to 3.6 v; unless otherwise speci?ed. symbol parameter conditions min. max. unit v ddd digital supply voltage - 0.3 +3.3 v d v ddd voltage difference between two supply voltage pins - 330 mv i ik dc input clamp diode current v i < - 0.3 v or v i >v ddd + 0.3 v - 10 ma i ok dc output clamp diode current output type 4 ma; v o < - 0.3 v or v o >v ddd + 0.3 v - 10 ma i o dc output source or sink current output type 4 ma; - 0.3 v < v o 1998 mar 10 21 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H timing characteristics note 1. c bus = bus line capacitance in pf. symbol parameter conditions min. max. unit serial digital inputs and outputs; (see fig.9) t r rise time t cy =50ns - 7.5 ns t f fall time t cy =50ns - 7.5 ns t cy bit clock cycle time 70 - ns t bck(h) bit clock time high t cy = 50 ns 17.5 - ns t bck(l) bit clock time low t cy = 50 ns 17.5 - ns t s;dat data set-up time host t cy = 50 ns 320 - ns t s;dat data set-up time i 2 s-bus input 10 - ns t h;dat data hold time host t cy =50ns 50 - ns t h;dat data hold time i 2 s-bus input 10 - ns t s;ws word select set-up time i 2 s-bus input t cy = 50 ns 100 - ns t h;ws word select hold time i 2 s-bus input t cy = 50 ns 100 - ns t d;dat data delay time host - 20 ns t d;ws word select delay time host - 15 ns i 2 c-bus timing; (see fig.10) f scl scl clock frequency 0 400 khz t buf bus free between a stop and start condition 1.3 -m s t hd;sta hold time (repeated) start condition; after this period the ?rst clock pulse is generated 0.6 -m s t low low period of the scl clock 1.3 -m s t high high period of the scl clock 0.6 -m s t su;sta set-up time for a repeated start condition 0.6 -m s t hd;dat data hold time 0 0.9 m s t su;dat data set-up time for standard mode i 2 c-bus system t su;dat > 250 ns 100 - ns t r rise time of both sda and scl signals f scl = 400 khz 20 + 0.1c bus (1) 300 ns f scl = 100 khz 20 + 0.1c bus (1) 1000 ns t f fall time of both sda and scl signals 20 + 0.1c bus (1) 300 ns t su;sto set-up time for stop condition 0.6 -m s c l(bus) capacitive load for each bus line - 400 pf t sp pulse width of spikes which must be suppressed by the input ?lter f scl = 400 khz 0 50 ns 1998 mar 10 22 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H fig.9 timing definitions of the serial digital data inputs and outputs. handbook, full pagewidth t s;dat mgl326 t bck(h) t bck(l) t cy t r t f t d;ws t s;ws t h;ws ws output ws input data output data input bck right left lsb msb t h;dat t d;dat 1998 mar 10 23 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... fig.10 timing definition of the i 2 c-bus. handbook, full pagewidth mbc611 p s sr p t su;sto t sp t hd;sta t su;sta t su;dat t f t high t r t hd;dat t low t hd;sta t buf sda scl 1998 mar 10 24 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here in this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force land scape pages to be ... application information handbook, full pagewidth mgl325 SAA2505H v ssd v ddd v ddda v ssda reset + 3.3 v trst clki clko efo1 to efo6 efi1 to efi3 tdo tms tdi tck spdif spdif 47 nf 0.1 m f 1 m f 15 pf 0.1 m f 15 pf 10 nf 3.3 m h 4.7 k w 47 m f 40.5 mhz sdbo3 sdb sdo3 wso3 scko3 sdo2 sdo1 sdo0 wso scko aclk sysclk sck ws sd dac lc/rc sysclk sck ws sd dac c/lfe sysclk sck ws sd dac ls/rs sysclk sck ws sd dac l/r sysclk sck ws sd spdif sysclk sck ws sd scki wsi sdi0 sdi1 sdbi adc 3 : 1 75 w sda scl addr standalone sysclk sck scl sda i 2 c-bus from microcontroller fig.11 application diagram for SAA2505H. 1998 mar 10 25 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.10 2.75 2.55 0.25 0.45 0.30 0.23 0.13 14.1 13.9 0.8 17.45 16.95 1.2 0.8 7 0 o o 0.16 0.10 0.16 1.60 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.03 0.73 sot393-1 ms-022 96-05-21 97-08-04 d (1) (1) (1) 14.1 13.9 h d 17.45 16.95 e z 1.2 0.8 d e q e a 1 a l p detail x l (a ) 3 b 16 y c e h a 2 d z d a z e e v m a 1 64 49 48 33 32 17 x b p d h b p v m b w m w m 0 5 10 mm scale pin 1 index qfp64: plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 x 14 x 2.7 mm sot393-1 a max. 3.00 1998 mar 10 26 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. 1998 mar 10 27 philips semiconductors preliminary speci?cation digital multi-channel audio ic (duet) SAA2505H definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011. internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca57 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 160 1010, fax. +43 160 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 545102/1200/01/pp28 date of release: 1998 mar 10 document order number: 9397 750 02979 |
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